The present invention relates to a semiconductor device and a manufacturing technique thereof and, particularly, to a technique effectively applied to manufacture of a semiconductor device having an interlayer insulation film with low dielectric constant between wiring layers.
For example, in a semiconductor device including an organic insulation film with low dielectric constant and with low hardness and low elasticity as an interlayer insulation film between wiring layers, there is a technique in which, since a dummy wiring and a connection hole are provided under a bonding pad, destruction of the interlayer insulation film and boundary separation between the wiring layers and the interlayer insulation film are prevented at the time of wire bonding to the bonding pad (for example, see Japanese Patent Laid-open No. 2001-267323).
Further, in a semiconductor including an organic insulation film with low dielectric constant, as an interlayer insulation film between wiring layers, which is lower in strength and adhesion properties than an inorganic insulation film, there is a technique in which: an opening corresponding to an electrode pad (bonding pad) is formed in each of a plurality of interlayer insulation films; the respective openings are filled with a metallic material to form a laminated body having metallic-film patterns; the laminated body having the metallic-film patterns is used as the electrode pad; and thereby durability of impact at the time of wire bonding to the electrode pad is improved (for example, see Japanese Patent Laid-open No. 11-340319).